Recently, as designed to better meet the demand for higher integration and high-speed operation of semiconductors and semiconductor related products, the dimensions of a given transistor forming a unit cell in a semiconductor memory apparatus have been reduced.
According to such a trend, the gate length of a transistor has been shortened. To better accommodate shorter gate lengths, the gate of the transistor may be directly coupled to a power supply voltage VDD or ground voltage VSS in some cases.
As discussed here, when the power supply voltage VDD or ground voltage VSS is directly coupled to the gate of the transistor, a gate oxide may be broken by power noise. In such an event, the overall reliability of the semiconductor memory apparatus may be degraded and/or compromised.